Harrison Xue Fei is a senior SI architecture in Lenovo CSP. He was a Technical Lead in Intel. He works on signal integrity of high-speed interconnect in server, storage, data center systems and desktop laptop. He published 20+ technical papers in technical conference and at Intel. He received his bachelor and master’s degrees in UESTC, Chengdu, China in 2002 and 2005 respectively.

Deng Lei has over 15 years of R&D experience in high-speed interconnects, antenna technology and high-performance RF system design. Currently, he is leading the team to develop cutting-edge solutions for next-generation connectivity. He holds a bachelor's and master's degree from Huazhong University of Science and Technology.

Dr. Jiangqi was an intel Principal Engineer on advanced packaging, power integrity, power delivery and associated server hardware engineering. He was the founder and the director of hardware research lab and technical vice president for Huawei’s North America research institute. From 2019 he started up NINGBO Everstrong technology which is focusing on advanced materials for advanced packaging and high-speed interconnect. Dr. He published more than 50 technical papers and owns more than 80 U.S. patents. His recent interest is new materials to meet AI needs.

Loong Jin has over 15 years of professional experience in the high-speed connector and cable assembly industry, having planned and led the development of multiple product lines including SSIO, HSIO, and BP. He also possesses extensive experience in the application and practice of interconnect solutions.

Fazhi Liu has over 10 years of experience architecting and de-risking high-speed digital systems for data-centric applications. Provides technical leadership across the entire product lifecycle, from initial system architecture and material selection to production bring-up and failure analysis. Focused on the design and validation of PCIe Gen5/6 and 112G/224G PAM4 SerDes channels, alongside robust Power Integrity implementation to ensure system-level performance.

Jinshan Ma, specializing in the server industry, leads upstream and downstream product planning and R&D, driving technology implementation and product iteration. Possesses extensive cross-domain technical expertise, having previously worked at companies such as Moore threads, Sugon, and Zhongsheng Hongxin. Responsible for core tasks including GPU chip product planning, supercomputer system architecture design, and CPU chip system platform design, with comprehensive technical vision and practical capabilities spanning from chips and servers to supercomputing systems.

Sun Anbing has more than 15 years of experience in PCB/SI and is currently focused on the hardware system architecture design and new technology research of the next-generation data center switche

Xiangnan Sun is responsible for the packaging R & D and mass production operation of all the company's products. In the R&D part, he collaborates with the design team and is mainly in charge of the packaging and system SI of all the company's products, including package design, package and system SIPI simulation, thermal simulation, stress simulation, and package engineering. He is also responsible for the introduction of the company's chip packaging from NPI to mass production. In the operation part, he is mainly responsible for the mass - production shipment of all the company's products, production planning, production management, account reconciliation, and ERP system maintenance.

Yanwu Wang focuses on EDA solutions for signal and power integrity design, optimization, and system solutions. He has over 20 years of experience in high-speed SerDes and DDR design for computer and server products. Before joining Detool, he was responsible for high-speed system design and product development at multiple companies.

Graduated from Guilin University of Electronic Technology with a Bachelor's degree in Communication Engineering in 2015. Previously worked at a leading communication design company, responsible for the design and simulation of RF circuits and antennas for consumer electronic products. He joined in Kinwong in 2020 and be employed in a Senior Manager of R&D. Responsible for electromagnetic field analysis and design optimization of high-frequency and high-speed PCBs. Main research areas including high-speed interconnection modeling, simulation and measurement. This includes PCB material selection, stack-up design, material parameter extraction and design simulation verification.