Panel Discussion I
Addressing the Ever-Growing Challenges in High-Speed Interconnect Designs in the AI Era: EDA Perspectives
Join us at the WAI conference for an exclusive roundtable discussion featuring leading experts from the EDA of High Speed and High Bandwidth Interconnect. This session will offer deep insights into the latest innovations, technical Trend and future direction of EDA for interconnects, with a special emphasis on their applications in AI era, including Chiplet, data center, AI application, and supercomputing. The discussion will address the industry's unique challenges and evolving demands.
Key topics will include:
- Global and local Market Demands: EDA of high-speed and high bandwidth interconnects for Chiplet, data centers, AI systems, and supercomputing infrastructure.
- Innovative Solutions and Future Trends: Exploring cutting-edge solutions and technological advancements to meet the industry's demands.
We invite you to join this unique opportunity to connect with industry leaders and shape the future of EDA for high-speed and high bandwidth interconnect technologies.
Panel Chair
Bo Pu
TPC chair, International Workshop on Advanced Interconnects (WAI)
Dr. Bo Pu is the TPC chair of WAI. He was a Staff Engineer in charge of design methodology for AP, SerDes, HBM2/2E/3, DDR5 and GDDR6 from 14nm to 3nm as well as responsible for collaborating with Cadence and ANSYS in Samsung Semiconductor HQ, Korea. Then he joined Missouri University of Science and Technology, MO, USA as an assistant research professor. Currently He is the VP of DeTooLIC Technology. He published over 50 technical papers and holds 15 patents about high speed links and 2.5D/3D ICs.
He is the TPC chair and Member of the IEEE WAI, IEEE EMCS, IEEE APEMC, ISEMC and ACES. He was also awarded the 2014 URSI Young Scientists Award, 2022 APEMC Outstanding Young Scientists Award, and the 2020, 2021 Distinguish reviewer of IEEE Transactions on EMC, 2023 Outstanding Associate Editor of IEEE Access. Dr. Pu is a recipient of the Technical Achievement Award from IEEE EMC Society.
He is the TPC chair and Member of the IEEE WAI, IEEE EMCS, IEEE APEMC, ISEMC and ACES. He was also awarded the 2014 URSI Young Scientists Award, 2022 APEMC Outstanding Young Scientists Award, and the 2020, 2021 Distinguish reviewer of IEEE Transactions on EMC, 2023 Outstanding Associate Editor of IEEE Access. Dr. Pu is a recipient of the Technical Achievement Award from IEEE EMC Society.
Invited Panelist
Stanley Zheng
Director of External Cooperation Committee and Chief of Standards, EDA²
Stanley Zheng graduated from the Department of Computer Science at Fudan University and holds an MBA from Macau University of Science and Technology. He has served as Senior Engineer at Inventec, Engineering Manager at Phoenix Technologies, Technical Support Manager/Strategy Director at Intel, and Director of Semiconductor Industry Development at Huawei. His work experience spans OS development, BIOS/EFI development, chip technical support, marketing, ecosystem promotion, IP strategy, 7nm chip product development, and industry development. He is the only person in Intel China ever served as a global chip leader. He currently serves as the Director of External Cooperation Committee and Chief of Standards at EDA².
Michael Liu
Senior product director, Empyrean Technology
Michael Liu is the senior product director of Empyrean Technology. He has more than 10 years of experience in ASIC chip design, manufacturing, and packaging EDA software product development and management, focusing on the planning, development, and promotion of EDA products. He helps Empyrean build up a mature Analog/Mixed-Signal design flow, and expand it to the fields of other full custom design such as flat panel display, signal chain, memory, RF and optoelectronics. He is building a reliability design methodology for design-manufacturing collaboration and a PPAC-oriented design-manufacturing packaging collaborative design solution. The solutions are widely adopted by national and international leading design houses.
Haisan Wang
AE Director, Cadence
Haisan Wang is an AE director from Cadence Multi-Physics System Analysis (MSA) service AE team. He mainly focuses on performing high performance chip system design by co-design and co-simulation technology. Prior to joining Cadence, he worked at Sigrity and Huawei.
Kefei Zhang
Technical Marketing Director, Semitronix
Kefei Zhang has over 20 years of work experience in the field of chip design services and IP/EDA. Having worked in various positions such as design, product planning, and marketing promotion in multiple IPO companies.
He has successfully planned multiple video and IoT chips. He has rich experience in product management and technical marketing within the fields of chiplet, high- performance SoC, and IP.
He has successfully planned multiple video and IoT chips. He has rich experience in product management and technical marketing within the fields of chiplet, high- performance SoC, and IP.
Yin Sun
Vice President of Product Engineering, DeTooLIC Technology
Dr. Yin Sun heads the Product and Technology departments at Ningbo Detoolic Technology Co., Ltd. She holds a Ph.D. from Missouri University of Science and Technology, an M.S. from The Hong Kong University of Science and Technology, and a B.S. from Fudan University. Her research focuses on signal and power integrity in high-speed integrated circuit chips and packaging, as well as electromagnetic compatibility.
Ming Zhou
SIMULIA Electromagnetics Industry Process Senior Consultant, Dassault Systemes
Zhou Ming earned his Master of Engineering degree from Harbin Institute of Technology. He has long specialized in electromagnetic field simulation technology research and possesses rich engineering application experience, providing CST simulation guidance and technical support to major clients in the high-tech and automotive industries.
Haidong Zhang
Leading EM and Thermal Product Director, NineCube
Zhang Haidong is currently leading FEM Electromagnetic and Thermal Product line at NineCube. He has over 10 years of specialized experience in electromagnetic simulation tools. He obtained a master's degree from Shanghai Jiao Tong University in 2012.
Xiuguo Jiang
EDA SE&CSM Manager, Keysight
Xiuguo Jiang is the Great China EDA SE&CSM Manager at Keysight Technologies, where he focuses on Signal Integrity, Power Integrity, and EMC. He has more than 15 years of experience in Hardware and Signal integrity. Prior to joining Keysight Technologies, Xiuguo worked on system and component design. In recent years, he has been focused on the modeling of PCB, Package, and Components as well as some challenges of signal integrity and power integrity. He is the author of over 5 books on SI, PI, and EE. He operates WeChat Official Account as a founder. The follower is more than 60k. He holds 1 Chinese patent. He published 4 papers.