Dr. En-Xiao Liu
                                Senior Principal Scientist & Deputy Department Director, A*STAR,
                            Singapore
                            Adjunct Associate Professor, National University of Singapore
                             
                            
                                Title:
                                High-Speed Interconnects in Semiconductor Systems: Where Physics Meets Performance
                                Biography:
                                
                                    En-Xiao Liu is currently Senior Principal Scientist and Deputy Department Director at A*STAR Institute of High Performance Computing. He is also an adjunct Associate Professor at the National University of Singapore. His research interests are in the areas of computational electromagnetics, high-speed electronics and packaging, electromagnetic compatibility (EMC), and AI/ML applications.
                                    Dr. Liu received the team award of Singapore President's Technology Award (2019), ASEAN and IES Prestigious Engineering Achievement Award (2019), and the IEEE EMC Society Technical Achievement Award (2016). He was an IEEE EMC Society Distinguished Lecturer, the past Chair of the IEEE EMC Singapore Chapter, and TPC/General Chair for several international conferences. He is an Associate Editor of four IEEE journals (T-EMC, T-SPI, L-EMCPA, and T-CPMT). He co-edited the T-EMC (a) Special Section on Nature-Inspired Algorithms for EMC/SI/PI (2018) and (b) the Special Issue on AI/ML & Deep Learning for EMC (2024). He was a plenary speaker at the EMC Japan/APEMC Okinawa 2024 Symposium.
                                
                                Abstract:
                                
                                    As semiconductor scaling is knocking on the door of the physical limits, interconnects open a new window into the spotlight of realizing system speed, bandwidth, energy, and reliability. 
                                    In this dense and deep connection era, multi-GHz signalling amplifies loss, crosstalk, and electrical and electromagnetic as well as multiphysics interactions across chip, package, and board hierarchies. Signal integrity, power integrity, and electromagnetic compatibility (SI/PI/EMC) can only be better achieved through multi-parameter and multi-objective early co-design and co-optimisation.
                                    On one hand, advanced packaging, chiplets, and co-packaged optics create dense, multi-modal channels offering new hopes and new promises. On the other hand, AI and Machine learning (ML) are demanding even more from high-speed interconnects. 
                                    Can we leverage new physics, novel materials, heterogeneous architectures, AI/ML, and so on, to transform interconnects from passive links into active enablers of ultra-wide bandwidth, high-speed, energy-efficient, and robust systems?