Dr.Xiaoning Ye
                                IEEE Fellow
Senior Principal Engineer at Data Center Group
                                    of Intel Corporation
                             
                            
                                Title:
                                High-Speed Interconnect in Data Centers.
                                Biography:
                                Dr. Xiaoning Ye is currently a Senior Principal Engineer at Data
                                    Center Group of Intel Corporation, specialized in high-speed interconnects. He
                                    received his Bachelor’s and Master’s degrees in electronics engineering from
                                    Tsinghua University, Beijing, China, in 1995 and 1997 respectively, and Ph.D. degree
                                    in electrical engineering from Missouri University of Science and Technology in
                                    2000.
                                    Dr. Ye published over 100 technical papers in IEEE and other technical journals and
                                    conferences, with over 3600 citations. He holds 20 patents and a few more
                                    applications in the areas of high-speed signaling. He also led the development of
                                    two industry standards on interconnect characterization: IEEE 370, and IPC test
                                    method 2.5.5.14. Dr. Ye is currently serving as Vice President of Technical Services
                                    for IEEE EMC Society. He was Chair of the IEEE EMC Society Technical Advisory
                                    Committee from 2017 to 2020, and has been an Associate Editor of IEEE Transactions
                                    on Electromagnetic Compatibility since 2016. Dr. Ye received Technical achievement
                                    award of IEEE EMC Society in 2015, and was elevated to IEEE fellow in 2021.
                                
                                Abstract:
                                The data center is undergoing a profound shift from CPU-centric
                                    design to accelerated computing and generative-AI–centric architectures. The
                                    fundamental unit of compute is no longer a single server but a distributed system at
                                    rack and cluster scale. Achieving performance now hinges on massive data
                                    parallelism—and the interconnect has become the first-order constraint as system
                                    scale and bandwidth rise.
                                    This speech traces the evolution of high-speed interconnects in modern data centers
                                    and explains why signal integrity now drives the ecosystem. We will also show how
                                    hardware-architecture innovations can relieve interconnect bottlenecks and unlock
                                    scalable performance.